22 feb
Reconocida empresa
Estado de México
Senior Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL Are you a Senior Verification Engineer looking for your next challenge?
Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL?
Want to join a very exciting Spain-based semiconductor company?
If you can say yes to this, then please keep reading.
We're partnered with a genuinely exciting Barcelona HQ'd semiconductor organization, and they're seeking a number of Senior Verification Engineers to join them on a permanent basis, working fully onsite in central Barcelona.
This company has some very aggressive growth plans and needs to hire at least 20 engineers over the next 18 months.
Visa sponsorship is available if needed, not to mention free Spanish lessons to help you assimilate in Spain.
International applicants are encouraged.
Required Skills: MSc or PhD in a related field 10 years relevant experience Proficiency in SystemVerilog and UVM Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools Experience with simulation and simulation tools Knowledge of revision control methodology and tools (git, svn) Experience in block level and sub-system or top-level verification Experience with formal and dynamic verification Strong problem-solving skills and attention to detail Excellent communication and teamwork abilities In return, you'll receive an excellent yearly salary, flexible work schedules, and very good career progression while working within a team of extremely talented individuals.
If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your resume.
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Muestra tus habilidades a la empresa, rellenar el formulario y deja un toque personal en la carta, ayudará el reclutador en la elección del candidato.